FSM works but there is sth wrong Please help

[tryingsth]

Hello,

I use a state machine. But the machine is in 2 for loop. My problem is the state machine work correctly but it calculate the last elemnts of loop. I want to get all values from loop.

To be clearly I shared my code
This part my begining



FOR i IN 1 TO n LOOP
FOR j IN 1 TO n LOOP




CASE pr_state IS
WHEN st0 =>

IF(counter = 0 ) THEN

s1<=adder(matris_in(i-1,j-1),matris_in(i-1,j));
s2<=adder(matris_in(i-1,j+1),matris_in(i,j-1));
...
...

This part is my aim.I want to get outputs value for every value of i and j. But at this moment I only get value for all output matris's value that i=n j=n
I hope I can explain.

matris_out(i-1,j-1)<=tmp5;
--finish<='1';

end loop;
end loop;


Please help for my final project.
Thanks

 

[FvM]

I presume a misunderstanding of VHDL iteration loop operation. It's defining parallel operation, not a sequence in time. Any signal assigned in the loop will be updated after the end of the respective process.

Your code snippet is omitting the important details, however.

As a general suggestion, review your VHDL text books about the nature of loop constructs.

The discussed problem doesn't seem to be related to FSM, by the way.

 

[tryingsth]

but I used the loops in 'process'.

PROCESS(pr_state,counter,clk)

BEGIN
counter <= 0;

FOR i IN 1 TO n LOOP
FOR j IN 1 TO n LOOP




CASE pr_state IS
WHEN st0 =>

IF(counter = 0 ) THEN

s1<=adder(matris_in(i-1,j-1),matris_in(i-1,j));
s2<=adder(matris_in(i-1,j+1),matris_in(i,j-1));
....

Do I share all code?