shaiko
Advanced Member level 5
Hello,
FSM A is designed using a single VHDL process - hence it's completely synchronous.
FSM B is designed using a 2 VHDL processes - hence it's outputs are combinatorial.
In theory, FSM A should allow higher Fmax... but (as an experiment) what if we register the outputs of FSM B ?
Is it safe to assume that both FSMs will have the same Fmax ?
FSM A is designed using a single VHDL process - hence it's completely synchronous.
FSM B is designed using a 2 VHDL processes - hence it's outputs are combinatorial.
In theory, FSM A should allow higher Fmax... but (as an experiment) what if we register the outputs of FSM B ?
Is it safe to assume that both FSMs will have the same Fmax ?