A purely serial implementation of an 8-bit adder would likely use less power than the parallel implementation (less states, registers, logic, and therefore transitions). It matters more about how much logic there is and how efficient the design is. So your question is beyond terrible, it's unanswerable due to the lack of any useful constraints on how the design gets implemented. I can make an enormous carry look ahead adder (for 8-bits) that makes the logic utilization go up dramatically and therefore the power consumption.
This homework question is rubbish, and whom ever gave it to you shouldn't be working as an instructor.