FSM: Relation between number of States and Power

[dhanya22]

Hi

I have a code in which I am using FSM.
Basically it is an adder having two inputs, a (8 bit ) and b (8 bit).

What I am trying to do is add a nd b.
Here I am using state machine, such that
1) 8 bit addition in 8 states.
2) 8 bit addition in 4 states i.e 2 bit addition in 1 state means I am still doing 8 bit addition but number of states are 4
and so on till I am executing
3) 8 bit addition in 1 state.
Hope I have made it clear.
The result is that for 8 bit addition in 8 states Power consumed is Maximum
and for 8 bit addition in 1 state power is minimum.

So now my question is what is relation between number of states and Power in FSM ? and it depends on what factor

Regards

 

[mrflibble]

Sounds a wee bit like a homework question. Anyways, forget the FSM. Ask yourself: "what does power usage in general in an fpga design depend on?". You should know that at least. If you don't know, then go read a book / a Xilinx guide on the subject. And if you do know, then you can reason your way to the answer for the FSM in easy enough steps...

 

[TrickyDicky]

This is a rather terrible question.
Power consumption cannot be determined directly from the RTL code, as the synthesisor will probably perform lots of optimisations. Plus there are synthesisor options to optimise for power, area or speed.

So, terrible question.

 

[dhanya22]

O.K

What I know is that it depends on switching activity , and the number of flip flops used.So the thing I have done here belongs to which encoding style can we call it one hot encoding ?

 

[FvM]

the thing I have done here belongs to which encoding style

A question that could be possibly answered if you show your code.

 

[ads-ee]

A purely serial implementation of an 8-bit adder would likely use less power than the parallel implementation (less states, registers, logic, and therefore transitions). It matters more about how much logic there is and how efficient the design is. So your question is beyond terrible, it's unanswerable due to the lack of any useful constraints on how the design gets implemented. I can make an enormous carry look ahead adder (for 8-bits) that makes the logic utilization go up dramatically and therefore the power consumption.

This homework question is rubbish, and whom ever gave it to you shouldn't be working as an instructor.