Dear friends,
Thanks for your response.. Dear rahdirs: From Xilinx blockset System Generator generates HDL codes in Simulink environment. This will provide VHDL project and then I open this file with ISE software. From here, I will synthesize the XST after specfying the outputs pins (LEDs). From using hdllib command, I see which blocks are synthesible in FGPA. 'From workspace block' is not synthesible. By the way, as an Example I use HDL counter (matlab says it is a synthesible block in Simulink) and use the same procedure, It does not work again!!!! So what should I do to get the workspace data from Matlab to process in FPGA blockset?
Dear dpaul;
I did not use a test bench. I have a Xilinx spartan 3E Xc3s1600E fg 320 FPGA board and use ISE software. I just wonder that do I have to use gateway in block to get data from Matlab workspace? Because whenever I use gateway in block with any simulink block, I observe nothing on output (8LED on FPGA). Again, what sould I do ?
Thanks..
Hitx