frequency synthesizer phase noise simulation

[hmsheng]

Deal all,

Do you know how to simulate phase noise of frequency synthesizer?

I simulate it with @DS linear method, but the simulate result is 10dB better than measured result.

In phase noise simulation, all blocks phase noise are included (they are crystal oscillater, reference divider, PFD/CP, LPF, VCO, loop divider). The simulated in-band phase noise is -90dBc/Hz, but the measured in-band phase noise is -80dBc/Hz.

Can someone tell me what cause the difference between simulated and measured results?

Best regards,
hmsheng

 

[boy]

it might be an incomplete transistor model in your crystal model. Some models dont include phase noise parameter. (it specifies as an exponent in the model but it is set to 1 (or 0) for most models )

 

[h0op]

i think boy is correct ,according to the transistor type u r using the noise may not by incooperated witn the model u can check that by looking up the noise parameters in the transistor model u r using.

 

[hmsheng]

Thank you all!

I've find the reason of high in-band phase noise. It's not the problem of devide model, but the noisy VDD of crystal oscillator! A bypass capacitor solves the problem.