Logic gates only dissipate heat when output transition happens. The transition time (duration under a logic gate's output can change) is constant, depends on Cgs and Ron (the process or technology).
Ratio of transition time and clock time period arises when the clock frequency increases. If the ratio is higher, the dissipated power is higher, because the logic gates spend more percentage of a time period in output transition.
The ratio can't be higher than ~0.25, otherwise the gates won't have enough time to change output value. This limits the frequency theoretically, practically they will produce too much heat under this ratio, which would require more cooling, bigger heatsinks, which is not possible in most of the cases, and other delay problems would occur, like race condition between lines.