frequency divider question

[nickwang]

Hi, experts,
I have couple of questions regarding divider designs:
1. What's the main operating frequency for modern dividers ? > 2g?

2. Is the divider output a squre wave ? Is it required that the high level time equal to low level time ? If not , what's purpose of this type of divider ?

Thanks for any suggestions.

 

[vfone]

Hittite is one of the biggest manufacturer of microwave dividers. Take a look to their dividers and you can get more information.

https://www.hittite.com/index.cfm?b...source=leftnav&subID=95,96,97,98,99&subHead=8

 

[nickwang]

thanks vfone;
If anybody can give me some information on where an non-equal during time of high level and low level, I'll appreciate your help.
(I should say other than 50% duty cycle)

Regards.

 

[jlee]

Non-50% duty cycle only means the output has even harmonics. 50% duty cycle square wave only has odd harmonics.

Operating frequency of frequency divider depends on application. PLL needs a frequency divider.

And frequency divider output is not necessary sqaure wave. It depends on what type of frequency divider you are using. For example, digital static frequency divider would output a squre wave, while Miller divider or injection-locked divider would output fundamental sine waves. Of course, conversion between square wave and sine wave is simple:
Sine -> Square : adding a inverter buffer at output;
Square -> Sine: Adding a lowpass filter at output.

 

[nickwang]

thanks jlee. It helps.
Furthermore, is it a deisgne issue if I can not get 50% duty cycle for a square wave divider?
Is it a good practice to always generate 50% duty cycle output ?

Anyway, thanks all.

 

[jlee]

Again, 50% duty cycle or not depends on the application...
But in most situations, I don't think it matters. For static frequency divider, the thing we concern is the rising edge or falling edge, not the duty cycle.