pyrite
Member level 2
verilog frequency divider
HI,
How to model a frequency divider or multiplier with verilog-A?
I have an input clk signal and I want to write a verilog-A model that can output different clock frequency based on the input clk frequency and the multiplier/divider value that user input.
I have been trying for awhile but couldn't get it to work. Can someone show me an example?
THanks
Jeff
HI,
How to model a frequency divider or multiplier with verilog-A?
I have an input clk signal and I want to write a verilog-A model that can output different clock frequency based on the input clk frequency and the multiplier/divider value that user input.
I have been trying for awhile but couldn't get it to work. Can someone show me an example?
THanks
Jeff