Apr 16, 2010 #1 J jason7361 Newbie level 4 Joined Apr 14, 2010 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,317 Can anyone give me a divider which frequency equal clock divider by 2 in Verilog? The divider will create by a D flip flop. Thank you.
Can anyone give me a divider which frequency equal clock divider by 2 in Verilog? The divider will create by a D flip flop. Thank you.
Apr 16, 2010 #2 M mux_master Member level 1 Joined Feb 25, 2010 Messages 37 Helped 5 Reputation 10 Reaction score 1 Trophy points 1,288 Location Minnesota Activity points 1,490 Simply invert the output on each clock cycle: always @(posedge clk) q <= ~q;
Apr 16, 2010 #3 P pavan.ps Newbie level 5 Joined Sep 17, 2008 Messages 9 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,318 always@(posedge clk or negedge rst) if(rst) q<= '0'; else q<= ~q;