Firstly, you are going to have to decide what the actual design problem is. I think it is more likely that there is a typo on your diagram (i.e. should be 50 MHz rather than 50 mhz). 50 mHz and 75 us makes no sense, nor does 50 mHz and 20 seconds.
Secondly, I did explain how you can write Verilog code for this. This is a very simple Verilog exercise, and you should be able to find several examples in books, tutorials and on the internet. Take a shot at writing it and then ask specific questions if you get stuck.
r.b.