The Miller capacitor and "zero resistor" values probably want
exploring. Not clear which version of the amplifier you mean
to go forward with, but CMOS op amps seem to like a zero
resistor in the Miller feedback to keep it from being -too- strong
as frequency rises (this is how you push out BW after getting
basic stability in hand).
Using a fixed resistor for the zero is a poor choice as it adds
variability on top of the MOSFETs, unrelated to them. A MOS
resistor stands some chance of tracking other devices. But
that is a secondary concern.
If it were my amplifier I'd just start with a nested parametric analysis
varying the R and the C (probably by octaves) to map out the
stability variation in search of the "sweet spot".
Of course I'd be doing that on a circuit whose operation was
generally satisfactory in DC aspects such as AVOL, output drive,
systematic offset voltage etc. since "what stabilization requires"
depends on topology, sizing and bias.
And to that point, are you sure you've got a bias scheme that will
support those performance dimensions (and slew rate, BW)?
I see your output sink is biased by a generic source, so this is
not what I'd call a settled design. And there may be more of that,
that wants polished - hard to tell with MOS devices having no
attributes visible.