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[SOLVED] frequency compensation of 2 stage opamp

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Newbie level 4
Sep 22, 2022
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I am getting a zero in between two poles ,and the amplifier is highly unstable due to this and I have put resistor in series with the compensation capacitance to get the phase margin of 60 degree. But I'm facing difficulty in getting the desired phase margin.

I designed a two stage opamp and it was unstable and to overcome that miller capacitance was added, then also phase margin did not reach 60 degrees. Can anyone please help??


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The Miller capacitor and "zero resistor" values probably want
exploring. Not clear which version of the amplifier you mean
to go forward with, but CMOS op amps seem to like a zero
resistor in the Miller feedback to keep it from being -too- strong
as frequency rises (this is how you push out BW after getting
basic stability in hand).

Using a fixed resistor for the zero is a poor choice as it adds
variability on top of the MOSFETs, unrelated to them. A MOS
resistor stands some chance of tracking other devices. But
that is a secondary concern.

If it were my amplifier I'd just start with a nested parametric analysis
varying the R and the C (probably by octaves) to map out the
stability variation in search of the "sweet spot".

Of course I'd be doing that on a circuit whose operation was
generally satisfactory in DC aspects such as AVOL, output drive,
systematic offset voltage etc. since "what stabilization requires"
depends on topology, sizing and bias.

And to that point, are you sure you've got a bias scheme that will
support those performance dimensions (and slew rate, BW)?
I see your output sink is biased by a generic source, so this is
not what I'd call a settled design. And there may be more of that,
that wants polished - hard to tell with MOS devices having no
attributes visible.

Thank you very much for your reply. And I am new to circuit design and this is my first telescopic opamp design. As you mentioned to perform parametric analysis, I had done this earlier by varying Capacitance ,but it didn't fetch me any results. Although by adding miller capacitance which was supposed to increase the phase margin ,it decreased it further. Can you please help further??

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You are running much less current in your output stage than in your input stage. Replace your voltage biasing with current mirror / replica circuitry throughout, starting with M9 and M11.

Before you do any further simulation, do some calculation on what the gm of the first stage and the gm of the second stage should be. There are well-known equations for where the first and second poles of the amplifier will be.

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