Free Tcl/Tk Based Testbench Generator for VHDL/ModelSim

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mexico_mike

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vhdl testbench generator

Anyone interested in a single entity VHDL testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this.


Uploaded file: **broken link removed** tb_gen.tcl
 
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vhdl test bench generator

Thank you !!

 
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testbench generator vhdl

Thank you !!
It is good info.
 

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