Free Tcl/Tk Based Testbench Generator for VHDL/ModelSim

[mexico_mike]

vhdl testbench generator

Anyone interested in a single entity VHDL testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this.


Uploaded file: **broken link removed** tb_gen.tcl

 

[Guest]

vhdl test bench generator

Thank you !!

On 2002-03-05 02:12, mexico_mike wrote:
Anyone interested in a single entity VHDL testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this.


Uploaded file: **broken link removed** tb_gen.tcl

 

[formatrix]

testbench generator vhdl

Thank you !!
It is good info.