Thanks for your help. I've got the Razavi book stashed away somewhere so will dig it out and take a look.
Also, the jitter/phase noise/spurs issue is something I'll worry about once I've found a generalised solution.
Is there a test I can do to check whether or not the dual modulus divider is sufficient?
From what I've read, in a fractional-N PLL, the channel spacing, f_step, is dictated by f_step = f_ref / (2^K), where K = accumulator size in bits. Now, if f_ref is to be an integer division of the crystal frequency, f_xtal, and (2^K) can be 1, 2, 4, 8 … 32 … 64 ... etc., then for a channel spacing of 100 kHz and f_ref of 10 MHz, K = 13.29. Rounding this to 13 or 14 gives me a channel spacing of 1.22 kHz or 610.4 Hz, respectively. To get the exact 1 kHz frequency step, I'd need to divide the crystal by a non-integer value.
This is before I get to the fun part of finding N/N+1 division ratios which are guaranteed to land exactly on every required frequency point.
(Apologies if this is all wrong - I'm an RF guy by trade and have not had much experience with the digital side of things!)