FracN PLL phase noise problems and questions

[oinkoink88]

FracN PLL phase noise

I have some burning questions with regards to third order MASH sigma delta Frac N PLL design as follows:

For PFD comparison frequency of 20 MHz, I design the loop bandwidth of 300 KHz to limit the loop bandwidth to filter away the quantisation noise at high frequency offsets. The problem arise when I measure the PLL output phase noise for frequencies with fractional input =0 and fractional input not equal 0.

The closed in phase noise at 10 KHz and 100 KHz (within loop bandwidth) worsen by about 2-3 dB and 4-6 dB respectively for output frequencies with fractional input not equal zero versus with zero.

i.e

Phase noise offset 10 K 100K
Fractional Freq (2432MHz) -90 -93
Non Fractiona Freq (2400MHz) -93 -98

I think that the phase noise worsening at 100K is due to loop bandwidth too narrow resulting in less quantisation noise rejection at 100K but why is 10K offset worsen by 3 dB?

I am currently using the same divided clock (VCO/N) to connect to both PFD and sigma delta modulator. Will this problem be rectified if I invert the clock to sigma delta modulator ( to perform what some paper call noise isolation?)

Hope someone can help me. Thanks in advanced.

 

[swicap]

FracN PLL phase noise

I think maybe u should compare the quantization noise psd of the dsm with different input first.
btw: dsm dithered?

 

[rfasic]

Re: FracN PLL phase noise

The behaviout of your PLL seems quite 'normal'. It is pretty common that the inband phase noise is worsened when you enable the Fractional part (ie. using an input ≠ 0).
The inband noise is a combination of many differents contribution within the fractional pll.
One is from the fact that the sampling instance in the phase-detector is not a constant. That is, the time from your charge pump is enabled once until the next time it is enabled is changing from clock to clock, so you will have an unequal sampling which downconverts quantisation noise down to your inband frequencies.
Another one is from the non-linearities in the different blocks (phase detector/charge pump etc) which also cause the phase noise to fold down to baseband.
So you do have a lot of contributors, and you will probably be able to decrease them to some level by narrowing the bandwidth. But in an ideal world you had to prevent them where they come from. eg. design some more linear components (good luck with this..) and for the non uniform sampling some proposes a S/H switch in the output of the chargepump (but take care of the spurs this might introduce!).
Regarding your noise isolation then it is always nice to have steep edges on your phase detector input, but I guess that even though you share the signal then you probably have some buffers inside your phase detector. So putting in an inverter will probably just load your signal just as much as the sigma delta modulator does.
Well maybe I misunderstand the intention of the inverter... If you want to place the inverter to make some time difference between the sigma delta activity and to the time when the charge pump is active, then I have done a lot of experiments with that with no significant difference.

Finally regarding your chosen loop bandwidth I must say that it seems a bit high! If you want an idea of where the quantization noise breaks through your inband noise floor then Perrots nice program can give you a good indication https://www-mtl.mit.edu/researchgroups/perrottgroup/tools.html#plldesign.

Practical loopbandwiths are usually much lower. Both due to the quantization noise but also due to inband spurs. This is the reason that many have tried to make some 'bandwidth extension' to ease direct modulation.

 

[ebalboni]

Re: FracN PLL phase noise

A increse in low frequency noise when the fractional part is ≠is very common and due to the fractional noise "folding" into the lower frequency range due to nonlinearities in the diveder/phase-detector/chargepump. One way to reduce the effect is to add a very small bias to the phase-detector so it does not operate at exactly zero phase (whee the nonlinarity is worst). You can try adding a large resistor in shunt with the chargepump output to move it off the zero-phase point. Try moving the phase by about 45 degrees by adding a resistor that will take aboiut 25% of the chargepump current. Unfortunutly a resistor will only work at one voltage -0 what you ideall need is a current source so the phase shift is always 45 degrees. You can use a static current source set to 25% the chargepump current for that.