FPGS / CPLD Power consumption

[shhrikant1]

Greetings,

Why is the Power consumption in CPLD is 10 times more than FPGA , though the architecture is simple in CPLD & it is very complex in FPGA.

Thanks in Advance

 

[FvM]

It's not valid for all CPLD, only for the classical structure involving single transistor cross-point switches and load resistors and respective static power consumption. FPGAs are SRAM based and using CMOS logic with no static power consumption except leakage currents.

 

[shhrikant1]

It's not valid for all CPLD, only for the classical structure involving single transistor cross-point switches and load resistors and respective static power consumption. FPGAs are SRAM based and using CMOS logic with no static power consumption except leakage currents.

Thanks FVM