[FPGA Xilinx Virtex5] Clock Multiplexing "glitch-free&a

[nicoxp31]

bufgctrl

Hi,

I'm currently using a Xilinx dedicated-virtex5 primitive module for a clock multiplexing function called "BUFGMUX_CTRL".
During synthesis I faced several problems with this module which gave some bad performance in terms of clock timing.

This module is considered as a glitch-free 2:1 multiplexer, that's why I would like to use it.
I also tried to use a standard 2:1 Xilinx multiplexer called "BUFGMUX" (not dedicated for Virtex-5) but it uses too much BUFGCTRL and thus does not fit into the fpga after mapping.

Do you have an other solution to get a clean ("glitch-free") 2:1 clock multiplexer (on virtex5 or not) ?

Thank you,
Regards,
Jerome

 

[Gunship]

bufgmux_ctrl

Are you sure? I am using a Virtex5 also and I also
use BUFGMUX without any problem. I prefer that
one because it is simple. If you have a map issue
from BUFGMUX, you may have a problem else where. I can probably help you if you post part
of the code and the error portion of the map report.

 

[echo47]

verilog clock multiplexer

I too have used BUFGMUX_CTRL and BUFGMUX in Virtex-5 without any unhappy surprises.
Be sure you've installed the latest ISE service pack (currently 9.2i SP4).

 

[nicoxp31]

bufgmux virtex 5

Hi,

Are you using SynplifyPro for synthesis ? i am using it.
But there is a Warning in the synthesis reprot indicating that the BUFGMUX_CTRL :
@W: MT246 |Blackbox BUFGMUX_CTRL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)

I don't know if after then it has some impacts during PAR.

FYI; One last thing: I found a Xilinx retargeting guideline for Virtex5 FPGA indicating that if the design contains a BUFGMUX, then it is automatically retargeted to a BUFGCTRL.

Regards,
Jerome

Added after 54 minutes:

One other issue is that at some point, I get the following error during MAP:

ERROR:Pack:2310 - Too many comps of type "BUFGCTRL" found to fit this device.
ERROR:Map:115 - The design is too large to fit the device.  Please check the
   Design Summary section to see which resource requirement for your design
   exceeds the resources available in the device.  In particular check the
   non-slice resources since the slice counts may reflect the early termination
   of the flow.

   NOTE:  An NCD file will still be generated to allow you to examine the mapped
   design.  This file is intended for evaluation use only, and will not process
   successfully through PAR.
ERROR:Pack:2310 - Too many comps of type "BUFGCTRL" found to fit this device.

Indeed, the report file indicates a overmapped issue concerning the # of BUFGs/BUFGCTRLs:

  Number of BUFG/BUFGCTRLs:                     40 out of      32  125% (OVERMAPPED)
    Number used as BUFGs:                       31
    Number used as BUFGCTRLs:                    9

But it seems that there is no way to display in the report file a listing of all BUFGs and BUFGCTRLs found by the placer/mapper. Do you know if it is possible somehow ?

Thanks,
Regards
Jerome

 

[echo47]

clock multiplexing

Difficult to guess what's wrong without seeing source code. Are you trying to put 40 BUFGCTRLs into your design? Your FPGA provides only 32 of them. If you aren't trying to use 40 of them, then be sure you haven't put the BUFGCTRL instantiation into an HDL module that you are reusing 40 times. That's just a guess.

I'm not sure how to get a list of where it's trying to use them.

 

[nicoxp31]

virtex 5 bufgmux

Hi,

No, the thing is that i'm not instanciating any of these BUFGCTRLs...the PAR tool may replace some other Xilinx standard modules by this BUFGCTRL automatically..because I am only instanciating either BUFGMUX_CTRL, BUFGMUX or BUFG in my verilog files.

Well, I will try with the latest ISE9.2i since i am still based on the ISE9.1i but I'm afraid that the problem will stay there after then.

Thanks anyway,
Regards,
Nicolas

 

[Abdul Haleem]

Re: [FPGA Xilinx Virtex5] Clock Multiplexing "glitch-fr

@nicoxp31: Even I have faced the same problem. If you have a clock gating module in your design, the Synplify tool automatically inserts a global clock buffer.

But the question is if a person has more than the stipulated 32 clock buffers in his design, how can it be mapped to the FPGA? Are there any local clock buffers also which can be used for internal clock gating modules?

Or can MUX be used for local clocks which do not have high fanout, though it is not advisable.
Can anybody help me out?

Thanks,
Haleem