[FPGA xilinx] UCF/NCF constraint files ?

[nicoxp31]

fpga ucf

Hi,

I have a NCF constraint file generated after synthesis (using synplify pro) and after this, i am using the Xilinx ISE design flow (NgdBuild, Map & PAR) to finally get the netlist to put on the FPGA.
The problem is that the ISE flow is requesting a UCF File that I need to write down my clock constraints (for instance)...so then these constraints will basically overwrite all the pre-generated constraints in the NCF file for the same clocks..
However, sometimes there are some errors during the Build since after synthesis the name of clock changed in the NCF file, so I would need to know if there was an automatic way to translate the NCF file into a UCF file ?

Is the NCF File really necessary for the ISE tools ?

Thanks,
Kind regards,
Jerome

 

[supercst]

xilinx ise ucf file

If you use GUI, the ncf with same name of the netlistfile and in the same directory will be automatically used by ISE