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Fpga wake up

KingMoshe

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Hi,
When my fpga got 3.3v it take 28mS untill fpga wake up and the internal clock start working.
During this 28mS my output gpio get unvalid value of 0.9v even though the IO pulled down as can see in the picture. Any idea why during wake up the IO is not absolute LOW?
GPIO is defined push pull mode.
 

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barry

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I don’t see any pull-down in the picture. Nor do i see any description of what those 3 traces are. Unless you’ve got external pull downs, this is totally expected behavior.
 

KingMoshe

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Hi,
When my fpga got 3.3v it take 28mS untill fpga wake up and the internal clock start working.
During this 28mS my output gpio get unvalid value of 0.9v even though the IO pulled down as can see in the picture. Any idea why during wake up the IO is not absolute LOW?
GPIO is defined push pull mode.
Red line - 3.3v FPGA VCC
Blue - FPGA internal Clock
Yellow - output signal from FPGA.

The question is why before the clock start, I see middle value for the output signal.
The signal have external pull down resistor
 

KlausST

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Hi,

most FPGAs are empty on power up. All I/Os are on default state (read FPGA documentation).
After power up they read their configuration from external memory. This takes some time. (maybe in your case the 28ms)
When you defined "clock" and some "outputs" ... then they are not valid immediately after power up, they are valid after the configuration is loaded.

If you want to get valid signals much earlier, then you need to do this
* either with external pullup / pulldown
* or using the FPGA´s line that tells whether the FPGA is configured or not.

For example if you have a microcontroller to communicate with the FPGA, then
* you can either generate a mcu_reset from the FPGA_ready (or similar name) = safe method
* or use a software_poll to wiat for the FPGA to get ready
* or just use a software delay (least safe method)

Klaus
 

KingMoshe

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Hi,

most FPGAs are empty on power up. All I/Os are on default state (read FPGA documentation).
After power up they read their configuration from external memory. This takes some time. (maybe in your case the 28ms)
When you defined "clock" and some "outputs" ... then they are not valid immediately after power up, they are valid after the configuration is loaded.

If you want to get valid signals much earlier, then you need to do this
* either with external pullup / pulldown
* or using the FPGA´s line that tells whether the FPGA is configured or not.

For example if you have a microcontroller to communicate with the FPGA, then
* you can either generate a mcu_reset from the FPGA_ready (or similar name) = safe method
* or use a software_poll to wiat for the FPGA to get ready
* or just use a software delay (least safe method)

Klaus
Doe's it make sense this is the reason that signal not absolutely zero?
During FPGA wakeup time Input is not defined so PMOS and NMOS a bit conducting due to the weak pullups with HIGH resisting.
The external pull down resistor create the route I draw with the blue arrow and voltage divided between the PMOS and the external pull down when a small part of the voltage fall on the external pull down
1657005984195.png

Thanks,
Moshe
 

dpaul

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Adding to what Klaus has mentioned.......use a Flash based FPGA (e.g. Microchip FPGA).
 

KlausST

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During FPGA wakeup time Input is not defined so PMOS and NMOS a bit conducting due to the weak pullups with HIGH resisting.
Hi,

Is this what the datasheet says about "non configured I/O behaviour" or "power up I/O behaviour"... or is this just your conclusion?
There may be differnt I/O with different power up behaviour.

The FPGA documentation will be very exact, you just need to read it. We can´t do this for you.

Klaus
 

KingMoshe

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Hi,

Is this what the datasheet says about "non configured I/O behaviour" or "power up I/O behaviour"... or is this just your conclusion?
There may be differnt I/O with different power up behaviour.

The FPGA documentation will be very exact, you just need to read it. We can´t do this for you.

Klaus
From datasheet, but it is not so clear.
can someone explain?

The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 have reached VPORUP level defined
in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the
POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all
VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that
are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pulldown
to GND (some pins such as PROGRAMN and the JTAG pins have weak pull-up to VCCIO as the default functionality).
The I/O pins will maintain the blank configuration until VCC and VCCIO (for I/O banks containing configuration
I/Os) have reached VPORUP levels at which time the I/Os will take on the user-configured settings only after a
proper download/configuration.
 

KlausST

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Hi,

what exactly you don´t understand.

Btw: You are aware that you hide all detail informations about your application. Thus we just can guess and in best case refer to "usual behaviour". Detailed answers can only given when you give detailed informations.

* Every FPGA will behave differntly, thus it´s a good idea to tell us which FPGA exactly you are using.
* The same is for the IO pin you talk about.
* ...and you configuration. Not only how the I/O is configured in your code, but also whether you use internal RESET signals, global_ENABLE ... or whatever your FPGA provides. And also how your FPGA becomes configured. What interface, timing....
* And last-but-not-least your schematic is important..

Klaus
 

FvM

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Except for very low complexity devices, even flash based FPGA have a certain boot time because an internal serial flash needs to be copied to RAM. I'm sure the answer to your question can be found in the datasheet. E.g. the FPGA has default weak pull-up for unconfigured outputs, there's a specification for the pull-up resistor range, also a specification for boot time.

I expect that 10k is much too high resistor value to guarantee logic low level during configuration time. The maximal value for Intel FPGA is rather 0.5 to 1 k.
--- Updated ---

Alternatively, it's often possible to switch to default logic high level by using external pull-up instead of pull-down.
 

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