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FPGA synthesizing real numbers??

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amirintisar

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Hey Folks,
i am using a SPartan 3 and am trying to send data to the PC via a Datacard. The communication between the two is fine but there is a problem with the data coming in to the PC. I am using the verilog HDL with Xilinx ISE 6.3, and i have programmed the FPGA to send out an incrementing number from 0 to 100. When this data arrives at the PC, it is a much larger number, but it is incrementing. For example 321,322,323,324...u know what i mean !!. What is the reason for this??

Thanks !!!!!!!!
 

What is a Datacard? I searched Google, but too many hits.

Have you isolated the problem to the FPGA, the Datacard, or your PC (Windows?) program?
 

A datacard is something used to read in data (digital or analogue) from any external device, in my case digital. I have 16 bits leaving my FPGA and enterring the datacard. The datacard comes with dll's that you can call using VB,C++ and other higher level languages. Using these dll's, you can see all the incoming data from your Vb or C++ script. I am in the imaging business so i am generating images in my script. I know the datacard is working because it is being used by someone else who has it running perfectly.

I read a discussion on this forum once about someone mentioning that you have to use fixed point multiplication in FPGA's because they dont synthesize numbers. I cant find this discussion for some reason but i was wondering if anyone knew about this issue ??
 

Your datacard sounds like a parallel digital I/O card, such as from National Instruments.

I'm still not clear if you have isolated the problem to the FPGA or to the datacard/software. Have you written new software for the datacard that could be causing the problem?

I would use something like a logic analyzer to examine the FPGA output data, to see if it matches your FPGA HDL simulation. I hope you are using a simulator (such as ModelSim) to check your HDL.

I use Xilinx FPGA multipliers, but I don't know what you mean by "synthesize numbers". They multiply two 18-bit signed integers and output a 36-bit signed result.
 

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