FPGA Reading Sensor - need help with verilog or vhdl code

Thread starter roddyalan
Start date May 22, 2009

Status: Not open for further replies.

May 22, 2009

roddyalan

Junior Member level 1

FPGA Reading Sensor

Hi guys,

I want to feed 4 signals to a MUX (run on FPGA supplied clock), and then to a comparator, which feeds the 4 bits in series to an FPGA input. Will this work?

Can anyone advise me on how to go about making verilog or vhdl code for reading serial data - either SPI or otherwise.

Also, i need advice on synchronization techniques.

Thanks
AR

Status: Not open for further replies.

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FPGA Reading Sensor - need help with verilog or vhdl code

roddyalan

Junior Member level 1

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