Did you properly set up your timing constraints and did you check that the design meets those requirements?
Klaus
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
#create_clock -period 20 [get_ports CLOCK_50]
#create_clock -period 20 [get_ports CLOCK2_50]
#create_clock -period 20 [get_ports CLOCK3_50]
#create_clock -period 20 [get_ports CLOCK4_50]
Code:derive_pll_clocks -create_base_clocks derive_clock_uncertainty #create_clock -period 20 [get_ports CLOCK_50] #create_clock -period 20 [get_ports CLOCK2_50] #create_clock -period 20 [get_ports CLOCK3_50] #create_clock -period 20 [get_ports CLOCK4_50]
Could well be typo's creeped in, may have to check that. Thinking if you miss math by clocking it would be all the time.
Does the problem repeat with the same inputs? If yes then it's likely functional so try and simulate it. If it's random its more likely timing.
In standard SDC constraint format all those statements proceeded by # are commented out. That would mean you have no input clock constraint unless there is one above the derive_pll_clocks line. Besides that, any create_clock command should be before any derive command.
Did you properly set up your timing constraints and did you check that the design meets those requirements?
Klaus
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
#create_clock -period 20 [get_ports CLOCK_50]
#create_clock -period 20 [get_ports CLOCK2_50]
#create_clock -period 20 [get_ports CLOCK3_50]
#create_clock -period 20 [get_ports CLOCK4_50]
Unless the clocks are integer multiples of each other and phase and frequency locked you won't be able to reliably transfer multi-bit values across the clock domains, you will either have to use an asynchronous FIFO or build a clock domain crossing for the multi-bit value by holding the value to transfer static and send another single to indicate the data is static and can be captured in the other clock domain.
That's exactly the realization I'm having right now. I built the sample and hold to double flip flop. But it doesn't work because the clocks are mismatched to not even within an integer multiple of each other. I'm going to try and build the asynchronous FIFO, and soup up the clock so it's a multiple of 2,7306x.
Thanks!
If you use an asynchronous FIFO you don't need to ensure the clocks are integer multiples of each other. That's the whole point of using an async FIFO, otherwise why bother using a FIFO that requires more resources to implement, when a synchronous FIFO would work.
There are lots of ways to do this...if the clocks are known you can implement a circular buffer with a grey code counter. One side loads the buffer at the location pointed to by the counter. The other side takes from the buffer at a location a few counts away from what the counter says.
If the fast side is the one 'producing' the data you'll need to make the circular buffer multiple samples deep and make sure it increments the grey code counter at a rate slow enough to guarantee the slow side sees changes.
This solution may be somewhat inflexible in terms of clock frequencies (or requires an over-sized buffer), but avoids bidirectional handshaking.
is meaningless for us as long as we don´t have values.The clocks are too close together
BTW, this is why so many people always suggest that a design uses a single clock domain everywhere. Only at the final interfaces between the FPGA core logic and the interface to the outside world that requires that interface to run off a clock asynchronous to the core logic, will you have a clock domain crossing.
module Pretty_useless_example_code (
input fc, //fast clock
input sc, //slow clock
input [7:0] frame, // S&H frame page
input signed [23:0] value,
output reg signed [23:0] out
);
reg oc1 = 1'b1;
reg oc2 = 1'b1;
reg [2:0] counterF;
reg [2:0] counterS;
reg signed [23:0] array [2:0];
always @ (posedge fc)
begin
if (([COLOR="#FF0000"]frame == 8'd1[/COLOR]) && (oc1 == 1'b1))
begin
array [counterF] = value;
counterF = counterF + 1'b1;
oc1 = 1'b0;
end
else if (([COLOR="#FF0000"]frame == 8'd9[/COLOR]) && (oc1 == 1'b0))
begin
oc1 = 1'b1;
end
end
always @ (posedge sc)
begin
if (([COLOR="#FF0000"]frame == 8'd3[/COLOR]) && (oc2 == 1'b1))
begin
out = array [counterS];
counterS = counterS + 1'b1;
oc2 = 1'b0;
end
else if (([COLOR="#FF0000"]frame == 8'd9[/COLOR]) && (oc2 == 1'b0))
begin
oc2 = 1'b1;
end
end
endmodule
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