FPGA Pin to Pin delay

[sankar.m8]

Friends,

Is there any way to calculate the pin to pin delay in an FPGA ? I am using Spartan 6 series.
I heard that the logic blocks are chosen by FPGA randomly during configuration and it is not in our control.
If that delay will be constant once it is calculated? or it will change on each power up? (Since FPGA load the mcs file on each power up)

Thanks in advance ..

 

[TrickyDicky]

it will be constant when the chip is compiled. Why do you need pin to pin delay? is it not a synchronous design?

 

[sankar.m8]

I have a critical signal which should have a fixed delay so that i can compensate the delay time. What do you mean by synchronous design?

 

[TrickyDicky]

synchronous design uses a clock to register signals through a design. Delaying signals to a specific time through an FPGA is almost impossible, as the time delay will vary with temperature.