FPGA performance testing application

[shra114]

FPGA performance testing application - temperature

Hi
I'm working on performance benchmarking of FPGAs, specifically how performance is affected by temperature. I'm using Spartan3E board. Anyone help me choosing the application which heats up the board and increases combinational delay effects the performance/accuracy of the application.

 

[permute]

Performance is specified over a range of temperatures and the tools are designed to place components in paths that will meet these specifications over that temperature range. Once you have a design, you cannot make changes and compare the new results to old ones -- the critical path may be different in each case. You would also need to operate the IC out of spec, >80C.

If you want to get the IC hot, simply make a design with all IO as SSTL DCI inputs (or SSTL2_II outputs...) The DCI features on older Xilinx parts implements SSTL outputs in a power-inefficient mode. (GTL/HSTL likely work as well). You might have to mix these based on the bank voltages.

Beyond that, you can just create some complicated, very pipelined, hashing function and use it to hash MB of data at a time and then output the results over some other interface. The hash can also be computed on a computer, and used to verify the results.

 

[aruipksni]

Re: FPGA performance testing application - temperature

Hi
I'm working on performance benchmarking of FPGAs, specifically how performance is affected by temperature. I'm using Spartan3E board. Anyone help me choosing the application which heats up the board and increases combinational delay effects the performance/accuracy of the application.

you can try put your board in a oven, or build one.

you can easily build an oven from shoe box,
power resistor, and dc power supply and some styrofoam, and temprature gauge (fluke).
after connecting your ps to resistor you can put your board in.
jist be carefull not to overheat the device ....