FPGA interface with H-Bridge Issue

[Ham23]

Hi all,

I have an issue where I can not figure out how to use the L298N H-bridge with a De0-Nano-SoC intel FPGA board through Verilog/VHDL. I am trying to drive multiple DC-motors using this H-bridge (https://www.robotshop.com/ca/en/multimoto-4-channel-h-bridge-speed-controller-arduino.html), but dont know how to write to M1/M2/M3/M4 or what the pin assignments will be. I currently have a PWM signal generated, but would appreciate additional help/source codes I could look at.

Thanks in advance.

Best regards,

 

[FvM]

The pin assignment has to be set according to the wiring between motor driver and FPGA board and the board schematic. You'll connect at least PWM, DIR and EN per motor, optionally SPI lines.
How do you want control the PWM?

 

[Ham23]

The pin assignment has to be set according to the wiring between motor driver and FPGA board and the board schematic. You'll connect at least PWM, DIR and EN per motor, optionally SPI lines.
How do you want control the PWM?

Well at the moment I just want to try and get the dc-motor spinning. I have both a Verilog and VHDL source code I am attempting to use. at the moment this is what I have to generate the PWM signal:

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Code VHDL - [expand]
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Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
 
Entity dcmotor1 is
Port (start,dir,clk:in std_logic;
pwm_out: out std_logic;
out_dc: out std_logic_vector(1 downto 0));
end dcmotor1;
 
architecture dcmotor_a1 of dcmotor1 is
signal clk1:std_logic;
signal div:std_logic_vector (24 downto 0);
begin
process (clk,start)
 
begin
if(start='0') then
div<="0000000000000000000000000";
elsif(clk' event and clk='1')then
div<=div+1;
end if;
clk1<=div(19);
end process;
process(clk1)
begin
if(clk1'event and clk='1')then
if start='0' then
out_dc<="00";
elsif start='1' and dir='1' then
out_dc<="10";
pwm_out<="1";
elsif start='1' and dir='0' then
out_dc<="01";
pwm_out<='1';
end if;
end if;
end process;
end dcmotor_a1;

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Once the PWM signal is generated through this, how do I send drive the dc-motor from it?

Thank you for your help.

 

[FvM]

I don't recognize a pwm generator. pwm_out is only set and never reset. Also don't use divided clock in FPGA design, use clock enable instead.

Motor pwm should have reasonable frequency between a few kHz and some 10 kHz, you usually want variable duty cycle. Just typing vhdl and pwm at Google gives many hits.