library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity event_detector is
generic ( event_vector_width : positive := 26 ) ;
port
(
rst ,
dsp_off : in std_logic ;
events : in unsigned ( event_vector_width - 1 downto 0 ) ;
dsp_on : buffer std_logic
) ;
end entity;
architecture synthesizable_event_detector of event_detector is
type fsm_states is
(
fsm_idle_state_0 ,
fsm_on_state_1
) ;
constant default_events_vector : unsigned ( event_vector_width - 1 downto 0 ) := "11100111110001111111111111" ;
signal fsm_state : fsm_states ;
signal event_flag : std_logic ;
begin
event_detecion: process
(
events ,
event_flag
) is
begin
for i in 0 to event_vector_width - 1 loop
if events ( i ) /= default_events_vector ( i ) then
event_flag <= '1' ;
else
event_flag <= '0' ;
end if ;
end loop ;
end process event_detecion ;
asynchronous_fsm : process
(
dsp_on ,
rst ,
fsm_state ,
event_flag ,
dsp_off
) is
begin
if rst = '0' then
dsp_on <= '0' ;
fsm_state <= fsm_idle_state_0 ;
else
case fsm_state is
when fsm_idle_state_0 =>
if event_flag = '1' then
fsm_state <= fsm_on_state_1 ;
dsp_on <= '1' ;
end if ;
when fsm_on_state_1 =>
if dsp_off = '1' then
dsp_on <= '0' ;
fsm_state <= fsm_idle_state_0 ;
end if ;
end case ;
end if ;
end process asynchronous_fsm ;
end architecture synthesizable_event_detector ;
process(rst, events, dsp_off )
begin
if rst = '0' then
dsp_on <= '0' ;
elsif events /= default_events_vector then
dsp_on <= '1' ;
elsif dsp_off = '1' then
dsp_on <= '0' ;
end if;
end;
Why?Presently, only the highest input bit is evaluated.
Why?
I want this code to compare all bits...What should I change to make it work ?
for i in 0 to event_vector_width - 1 loop
if EVENT_DETECTOR_EVENTS_I ( i ) /= default_events_vector ( i ) then
event_flag <= '1' ;
if mask_vector ( i ) = '0' then
unmasked_event_flag <= '1' ;
else
unmasked_event_flag <= '0' ;
end if ;
else
event_flag <= '0' ;
end if ;
end loop ;
end process event_detecion ;
for i in 0 to event_vector_width - 1 loop
if EVENT_DETECTOR_EVENTS_I ( i ) /= default_events_vector ( i ) then
event_flag <= '1' ;
if mask_vector ( i ) = '0' then
unmasked_event_flag <= '1' ;
else
unmasked_event_flag <= '0' ;
end if ;
else
event_flag <= '0' ;
end if ;
end loop ;
end process event_detecion ;
if mask_vector ( i ) = '0' then
unmasked_event_flag <= '1' ;
exit;
for i in 0 to event_vector_width - 1 loop -- where should the "exit" statement (or statements) be placed ?
if EVENT_DETECTOR_EVENTS_I ( i ) /= default_events_vector ( i ) then
event_flag <= '1' ;
if mask_vector ( i ) = '0' then
unmasked_event_flag <= '1' ;
else
unmasked_event_flag <= '0' ;
end if ;
else
event_flag <= '0' ;
end if ;
end loop ;
event_flag <= '0';
for ... loop
event_flag <= event_flag or condition;
end loop;
any_event_detected <= '1' when events /= default_events ;
unmasked_event_detected <= '1' when
( ( events ( 0 ) /= default_events ( 0 ) ) and ( mask_vector ( 0 ) = '0' ) ) or
( ( events ( 1 ) /= default_events ( 1 ) ) and ( mask_vector ( 1 ) = '0' ) ) or
( ( events ( 2 ) /= default_events ( 2 ) ) and ( mask_vector ( 2 ) = '0' ) )
else '0' ;
I never noticed confusion of a synthesis tools with these rather trivial behavioral constructs. My main concern would be 1. code readability and 2. shortness, as far as the first objective isn't thwarted.but I think the "exit" solution have a higher risk for confusion of the synthesis tool.
event_flag <= or_reduce((events XOR default_events_vector) AND NOT mask_vector);
shaiko said:I'll much appreciate if you show me the exact syntax to achieve that.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 event_flag <= '0' ; unmasked_event_flag <= '0' ; for ... loop if EVENT_DETECTOR_EVENTS_I ( i ) /= default_events_vector ( i ) then event_flag <= '1' ; if mask_vector ( i ) = '0' then unmasked_event_flag <= '1' ; end if ; end if ; end loop ;
Instead of setting the event flags directly in the loop, set variables that you clear before the loop and test after the loop.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 process(input) variable temp : boolean; begin temp := false; for i in 0 to 15 loop temp := temp or (input(i) = MY_TESTER(i) ); end loop; if temp then event_flag <= '1'; else event_flag <= '0'; end if; end process;
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