fpga design problems....???

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hi sir i tried in quartus with virtual pins n i got ans............thk uuuuuu very much.......
 

vitual pins are just a way for you to get an idea of resource usage for a single entity. You cannot get a working design using vitual pins.
 

vitual pins are just a way for you to get an idea of resource usage for a single entity. You cannot get a working design using vitual pins.

sir..thr is a provision in software where we cn give values for virtual pins as either on or off...ie..1 or 0...
with sme pins as input n sme as output n rest all as virtual cnt we get ans????
whether this ll b right or nt???
 

you would do that by connecting the inputs to 1 or 0. But this will have the effect of synthesising away large amounts of logic as the inputs are constant.

Virtual pins are not a solution to your integration problem. You still need a mecahnism to get the data in and out of the chip to allow your design to work.
 

I suggest to think of an interface, that would be also applicable to a real hardware design, e.g. a 32 or 64-Bit data bus with an address port to select individual registers and read and write strobes. Preferably as synchronous bus with a common clock.
 

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