FPGA Cyclone II + Quartus II -> LVDS and M4K RAM

[Sink0]

Hi, i have couple questions about using LVDS outputs and M4K RAM as a FIFO.

First of all, is there any license requirements to use any of both Mega-Functions?

Second... If i want to use x2 Serializer i dont need a dedicated PLL, but if i am using a PLL to generate clock to my blocks.. can i use same PLL to drive 5 x2 Serializers and Deserializers?

So far i was using a FIFO made by me with LEs, it is consuming lot of Logic, how much logic usualy a 9x64 FIFO may consume using M4K ram?

I might have couple more questions but thats all for now.

Thank you very much!

 

[FvM]

You don't need a license (except the general free Q.uartus web license) for the said basic MegaFunctions. A license
(respectively a Q.uartus subscription) is required for e.g. DDR controller, DDS, FIR filter.

You can clock multiple SERDES instances from a single PLL and one pair of PLL outputs, if they are using the same
clock source and frequency/phase parameters. A DESER is often clocked from an external clock source along
with the data (source synchronous operation), than it won't work.

The MegaWizard will inform you about the exact resource usage of a specific FIFO design. I guess, it needs < 100 LE in your case.

 

[Sink0]

FPGA Cyclone II + qu(at)rtus II -> LVDS and M4K RAM

Damn i am out of ideas... as i cant send the clock by cable i must encode the data with the clock.. but all external SERDES and DESER that i am looking at use a sync signal. i cant have that as most of the time the SERDES wont be talking with all the DESER becouse tranceiver will be on receive mode if it does not have to send anything... how the hell am i suposed to creat a M-LVDS Bus using low-end FPGAs like Cyclone II and Cyclone I? ANy sugestion please? I cant use Ethernet as you sugested on the other post becouse packages will be very small .. so ethernet got tooo much overhead fr small packages.

 

[Sink0]

FPGA Cyclone II + qu(at)rtus II -> LVDS and M4K RAM

Would this work?

**broken link removed**

Thats like some asycrounous oversampling with the same clock with a 90 degrees difference and sampling at rise and fall edge. Maybe could work for me using standard LVTTL to drive a M-LVDS tranceiver and receive onversampling data to decode Manchester code with another FPGA behind another M-LVDS tranceiver.. what do you think?