FPGA Common Issue: Clock generated by register...

[cj007]

I'm trying to figure out ->

What is the maximum frequency of clock,which is generated by register (not from oscillator/BUFG/DCM), can be feed into other registers as a clock and the design muz meet the timing?

I did 2MHz clock generated by register -> No timing issue.

How can we decide what frequency of clock (generated by regsiter) that we can supply to other register as clock?


Thanks for your sharing...

Moving Forward


Thanks.

 

[xtcx]

You can reach higher clocks upto the latency of your FF...Your register transfer\propagation delay limits the maximum clocking.....I used to divide 40 MHz and drive many sub-counters using that clock and my master clock is about 80Mhz...

 

[banjo]

The only real limit is the speed grade of the FPGA. I have done this in excess of 250 MHZ. If the register based clock feeds a lot of flops, then you need to use a global clock buffer to reduce the clock slew between the flops receiving the clock. Generally, I would instantiate the clock buffer explicitly in the HDL code.

If your register generated clock only feeds a few flops, then local clock routing is usually sufficient. If you spec your clock periods accurately in the constraints file, then FPGA place and route tools should configure the routes and placement to insure that your design works.