FPGA Board Files on VIVADO

[michaelScott]

Hello friends,
I obtained a FPGA card from chinese which brand name is ALINX. But i can not find it on VIVADO. I am looking for the board files(xml) on the website but i could not find it.
How can i find the board files. Can you help me about that.
Thanks in advance.

 

[barry]

1) Xilinx is under no obligation to support (questionable) third-party boards.
2) You get what you pay for. It's quite possible your ALINX board design is stolen from some other company, which is why there's no support there. Did you try contacting the manufacturer?

 

[dpaul]

Do want this info in order to create a new project?

If yes, then if you know the FPGA part number it can also be done. Just use 'Parts' instead of the 'Boards'.

 

[FlyingDutch]

Hello,

I agree with @dpaul, as I seen on their WWW page (ALINX), the producer provide a schematics for these boards. You should be able to make "user constarints" file by your own doing it manually(using provided schematics). I had the same situation for Chineese "Qmtech" boards with Xilinx Artix-7 FPGAs.

Best Regards

 

[michaelScott]

Hello,

I agree with @dpaul, as I seen on their WWW page (ALINX), the producer provide a schematics for these boards. You should be able to make "user constarints" file by your own doing it manually(using provided schematics). I had the same situation for Chineese "Qmtech" boards with Xilinx Artix-7 FPGAs.

Best Regards

Thanks for your reply,
I contacted with the manufacturer for the schematic. The "user constraints" files that you have mentioned are easy to do? Where can i learn this process? The reason is that I am pretty new at FPGA projects.
Thanks in advance

 

[KlausST]

Hi,

I guess it depends on the language and the tool you use. There may be several ways to do it.

For XILINX they use .ucf (user constraint file).
Open one with a text editor.

It does not matter what brand of board you use ... it´s urgent to tell the compiler software at which pin you connected which signal...

Klaus

 

[michaelScott]

Hi,

I guess it depends on the language and the tool you use. There may be several ways to do it.

For XILINX they use .ucf (user constraint file).
Open one with a text editor.

It does not matter what brand of board you use ... it´s urgent to tell the compiler software at which pin you connected which signal...

Klaus

Thanks for the reply. This board contains lots of pieces inside of it. Would not be too harsh to do it?

 

[barry]

The constraints file defines, at a minimum, pin location and IO type. You will have to figure out from the schematic whether it’s, for instance, 3.3V CMOS or LVDS. This CAN be done, but a reputable manufacturer would supply some other documentation along with the schematic.

 

[KlausST]

Hi,

Thanks for the reply. This board contains lots of pieces inside of it. Would not be too harsh to do it?

For a development board I expect the manufacturer to provide the constraints file.
But as soon as you add your own circuit you need to add it in constraints file.

And if you design your own board ... it´s urgent to do this on your own.

Harsh or not - it has to be done. But it´s not that difficult to become familiar. Then it´s not that harsh anymore.

Klaus

 

[ads-ee]

For XILINX they use .ucf (user constraint file).
Open one with a text editor.

A .ucf file was used by ISE. The constraint files with Vivado are .xdc (Xilinx Design Constraints), which are the Xilinx version of an .sdc (Synopsys Design Constraints) file

Thanks for the reply. This board contains lots of pieces inside of it. Would not be too harsh to do it?

It's not difficult to do. Below is a sample of what is in the first two sections of the Arty A7 master constraints file

## This file is a general .xdc for the Arty A7 Rev. D
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

# Clock signal
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK}];

# Switches
set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]

You will have to create a similar file based on the schematic if the Vendor doesn't provide one.

A description of what goes into an .xdc file can be found in the documentation: https://docs.xilinx.com/v/u/2021.1-English/ug903-vivado-using-constraints

 

[niciki]

I would suggest to look for github or gitlab repositories.

Have you checked e.g.: https://github.com/alinxalinx ?

 

[dpaul]

@michaelScott

The "user constraints" files that you have mentioned are easy to do? Where can i learn this process?

You want to learn how to constrain a design for Xilinx FPGAs.....follow this documentation.
https://docs.xilinx.com/v/u/2020.1-English/ug903-vivado-using-constraints (there might be a larest version of the UG903)

Upto the ISE tool Xilinx called them ucf file, from Vivado onwards they are called xdc files. Do not get confused with such naming schemes. Just remember that constraints files are a collection of TCL commands for the tools to interpret!

 

[KlausST]

Hi,

On my PCB layout software I wrote a script that prepares a constraint file.
* it adds connected pins with their pin name and the connected signal name
* it omits power supply pins
* it omits special pins

This is not a ready to use file, but it helps not to miss any pins in the constraints file and it prevents mistakes.
Still - before using it - one has to complete all the other informations (drive strength, IO type, speed...)

Klaus