found drc errors in cadence

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pavanucs

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hi all,
I am a newbie to cadence..
when i was designing layout for xor gate...i found the follwing drc errors
1.Nwell-stamp error float
2.p+SD to nwell distance<=10um

kindly help me out of these errors
thank you
 

pavanucs said:
1.Nwell-stamp error float
Click to expand...
N+tap (in Nwell) to VDD (metal) connection is missing.

pavanucs said:
2.p+SD to nwell distance<=10um
Click to expand...
Self-explaining: The p+ source & drain regions of the PMOSFETs need a distance ≧ 10µm to the nwell border
(due to doping inhomogeneity near the border).
 

erikl said:
N+tap (in Nwell) to VDD (metal) connection is missing.


Self-explaining: The p+ source & drain regions of the PMOSFETs need a distance ≧ 10µm to the nwell border
(due to doping inhomogeneity near the border).
Click to expand...

thanks a lot..erikl
it was very much helpful
 

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