Hi All,
please write out the svf file while doing rtl synthesis and read that svf file in the formality and do the verification then formality will pass becuse tool try to map the design according to the name of cell/net in the both rtl and netlist. svf will give the naming change that has taken place in the rtl cell/net names in the rtl while converting it to the netlist.
Regards,
Ramesh.S
Added after 1 minutes:
or use the following commands in the formality.
match
match -heir
match -datapath
Regards,
Ramesh