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Formal port/generic <> is not declared in--- ERROR!

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kaiserschmarren87

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Formal port/generic &lt;&gt; is not declared in--- ERROR!

Hello,

In the design which I am working on, I need to pass a std_logic_vector(15 downto 0) from a register in the top module to an input port of a sub module. I have done it in the following way:

Code:
-----top_module----
    signal ConfigMem_Wire : std_logic_vector(15 downto 0);
    {Register_module}
    register     => ConfigMem_Wire
    {sub_module_1}
    ConfigMem => ConfigMem_Wire

-------sub_module_1-----------
     ConfigMem : in std_logic_vector(15 downto 0);

     signal ConfigMem_Wire : std_logic_vector(15 downto 0);

     ConfigMem_Wire  <= ConfigMem ;

      {sub_module_2}
       ConfigMem => ConfigMem_Wire

-----------sub_module_2--------------
     ConfigMem : in std_logic_vector(15 downto 0);

     signal ConfigMem_Wire : std_logic_vector(15 downto 0);

     ConfigMem_Wire  <= ConfigMem ;


       {sub_module_3}
       ConfigMem => ConfigMem_Wire

       {sub_module_4}
       ConfigMem => ConfigMem_Wire

       {sub_module_5}
       ConfigMem => ConfigMem_Wire

--------------------------------------------------------------------------------

During Synthesis I get this error "Formal port/generic <configmem> is not declared in <sub_module_2>.....

I am routing the value correctly I guess.

I get this error when I have either top module is set as top module or sub_module_1 set as top module....

I am using Xilinx ISE 14.3 version.


Is there anything missing or wrong in port mapping method?

- - - Updated - - -

Hello,

In the design which I am working on, I need to pass a std_logic_vector(15 downto 0) from a register in the top module to an input port of a sub module. I have done it in the following way:

Code:
-----top_module----
    signal ConfigMem_Wire : std_logic_vector(15 downto 0);
    {Register_module}
    register     => ConfigMem_Wire
    {sub_module_1}
    ConfigMem => ConfigMem_Wire

-------sub_module_1-----------
     ConfigMem : in std_logic_vector(15 downto 0);

     signal ConfigMem_Wire : std_logic_vector(15 downto 0);

     ConfigMem_Wire  <= ConfigMem ;

      {sub_module_2}
       ConfigMem => ConfigMem_Wire

-----------sub_module_2--------------
     ConfigMem : in std_logic_vector(15 downto 0);

     signal ConfigMem_Wire : std_logic_vector(15 downto 0);

     ConfigMem_Wire  <= ConfigMem ;


       {sub_module_3}
       ConfigMem => ConfigMem_Wire

       {sub_module_4}
       ConfigMem => ConfigMem_Wire

       {sub_module_5}
       ConfigMem => ConfigMem_Wire

--------------------------------------------------------------------------------

During Synthesis I get this error "Formal port/generic <configmem> is not declared in <sub_module_2>.....

I am routing the value correctly I guess.

I get this error when I have either top module is set as top module or sub_module_1 set as top module....

I am using Xilinx ISE 14.3 version.


Is there anything missing or wrong in port mapping method?



I got the solution... Just had to declare the components for the respective modules....! Simple mistake though...
 

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