Nov 6, 2006 #1 D davyzhu Advanced Member level 1 Joined May 23, 2004 Messages 494 Helped 5 Reputation 10 Reaction score 2 Trophy points 1,298 Location oriental Activity points 4,436 logical equivalence check Hi all, When do Formal Equivalent Check (RTL and Gate Level) , I remember that the tool compare the comb logic between D-FF . But when synthesis use re-timing and gated clock, can LEC tool compare RTL and Gate? And is gated clock one form of re-timing? I am reading a paper from SNUG about gated clock (How to successfully use gated clock...) but I cannot understand the waveform... Best regards, Davy
logical equivalence check Hi all, When do Formal Equivalent Check (RTL and Gate Level) , I remember that the tool compare the comb logic between D-FF . But when synthesis use re-timing and gated clock, can LEC tool compare RTL and Gate? And is gated clock one form of re-timing? I am reading a paper from SNUG about gated clock (How to successfully use gated clock...) but I cannot understand the waveform... Best regards, Davy
Nov 6, 2006 #2 Q quan228228 Full Member level 4 Joined Mar 23, 2006 Messages 196 Helped 16 Reputation 32 Reaction score 3 Trophy points 1,298 Activity points 2,571 logic equivalence check davyzhu said: Hi all, And is gated clock one form of re-timing? I am reading a paper from SNUG about gated clock (How to successfully use gated clock...) but I cannot understand the waveform... Best regards, Davy Click to expand... Gated clock is not a form of re-timing, it is used for saving power. Can you show your waveform, and explain detailedly.
logic equivalence check davyzhu said: Hi all, And is gated clock one form of re-timing? I am reading a paper from SNUG about gated clock (How to successfully use gated clock...) but I cannot understand the waveform... Best regards, Davy Click to expand... Gated clock is not a form of re-timing, it is used for saving power. Can you show your waveform, and explain detailedly.
Nov 6, 2006 #3 A aravind Advanced Member level 1 Joined Jun 29, 2004 Messages 482 Helped 45 Reputation 94 Reaction score 18 Trophy points 1,298 Location india Activity points 3,597 synopsys lec in lec set flatten model -gated_clock will solve the problem
Nov 15, 2006 #4 R rameshsuthapalli Full Member level 3 Joined Jun 27, 2006 Messages 154 Helped 24 Reputation 48 Reaction score 7 Trophy points 1,298 Location bangalore,india Activity points 2,129 equivalent check Hi all, which tools u r using for synthesis and formal verification. regards, rameshs
equivalent check Hi all, which tools u r using for synthesis and formal verification. regards, rameshs
Nov 15, 2006 #5 R rsrinivas Advanced Member level 1 Joined Oct 10, 2006 Messages 411 Helped 50 Reputation 100 Reaction score 11 Trophy points 1,298 Location bengalooru Activity points 3,689 formal equivalency check synopsys dc formality
Nov 16, 2006 #6 R rameshsuthapalli Full Member level 3 Joined Jun 27, 2006 Messages 154 Helped 24 Reputation 48 Reaction score 7 Trophy points 1,298 Location bangalore,india Activity points 2,129 logic equivalent hi all, if u r using the synopsys DC and formality.the DC will give the SVF file as output while doing the synthesis.which will give the gudence to the formality.so that the logical equvalency for the rtl vs netlist will pass. regards, rameshs
logic equivalent hi all, if u r using the synopsys DC and formality.the DC will give the SVF file as output while doing the synthesis.which will give the gudence to the formality.so that the logical equvalency for the rtl vs netlist will pass. regards, rameshs
Nov 24, 2006 #7 B bravobravo Full Member level 2 Joined May 16, 2001 Messages 122 Helped 3 Reputation 6 Reaction score 2 Trophy points 1,298 Location USA Activity points 973 logic equivilant to exclusive -or gate HOw about design with ICG cells ?? like ICG cells from artisan ... ??
logic equivilant to exclusive -or gate HOw about design with ICG cells ?? like ICG cells from artisan ... ??