I don't know what synthesis tool you're using and I'm actually not looking at any synthesis tool manuals at the moment but I'll try to answer some of these.
1. The net area is probably a figure relating to the amount of routing resources used. I'm guessing this defined in the technology section of the library you're using and it's probably just an estimate detailed routing information isn't available just after synthesis.
2. It's probably the sum of the standard cell area, macro and memory area. Possibly the net area depending on the synthesis tool.
3. Memory and macro instances all contribute to the total area. Maybe halo and DRC area is included too?
4. Leaf cells are cells that can't be broken down any further. Like AND gates and INV gates. These take up real area on the chip die.
5. A summation of the sequential cells in the design: Flops, latches, etc.
6. The non-sequential cells: NANDs, BUFs, etc.
7. Hierarchical instances aren't physical cells but named logical partitions of the design.
Your synthesis manual should definitely have a detailed description of where it gets the figures it reports.
HTH