bachoo786
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Hello there,
I needed help with test bench. I am using a FOR loop for my test bench to evaluate values that are stored in a text file inside a LUT.
Here’s my VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
Entity ROM_ent is
Port(
ADDR: IN std_logic_VECTOR(7 downto 0);
CLK: IN std_logic;
DATA: OUT std_logic_VECTOR(7 downto 0)
);
end ROM_ent;
Architecture Behavioral of ROM_ent is
type rom_type is array (255 downto 0) of std_logic_vector (7 downto 0);
impure function InitRomFromFile (RomFileName : in string) return rom_type is
FILE romfile : text is in RomFileName;
variable RomFileLine : line;
variable ROM : rom_type;
begin
for i in rom_type'range loop
readline(romfile, RomFileLine);
read(RomFileLine, ROM(i));
end loop;
return ROM;
end function;
Constant ROM : rom_type := InitRomFromFile("Doc1.Txt");
begin
process (CLK)
begin
if(CLK'event and CLK = '1') then
DATA <= ROM(to_integer(unsigned(ADDR)));
end if;
end process;
end Behavioral;
Can anyone please show me the code for my test bench with a FOR loop in it for the VHDL code above?or at least guide me please?
Thank you!
I needed help with test bench. I am using a FOR loop for my test bench to evaluate values that are stored in a text file inside a LUT.
Here’s my VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
Entity ROM_ent is
Port(
ADDR: IN std_logic_VECTOR(7 downto 0);
CLK: IN std_logic;
DATA: OUT std_logic_VECTOR(7 downto 0)
);
end ROM_ent;
Architecture Behavioral of ROM_ent is
type rom_type is array (255 downto 0) of std_logic_vector (7 downto 0);
impure function InitRomFromFile (RomFileName : in string) return rom_type is
FILE romfile : text is in RomFileName;
variable RomFileLine : line;
variable ROM : rom_type;
begin
for i in rom_type'range loop
readline(romfile, RomFileLine);
read(RomFileLine, ROM(i));
end loop;
return ROM;
end function;
Constant ROM : rom_type := InitRomFromFile("Doc1.Txt");
begin
process (CLK)
begin
if(CLK'event and CLK = '1') then
DATA <= ROM(to_integer(unsigned(ADDR)));
end if;
end process;
end Behavioral;
Can anyone please show me the code for my test bench with a FOR loop in it for the VHDL code above?or at least guide me please?
Thank you!