for loop execution in vhdl

[melexia]

Hi
i am using for loop for converting gray code into binary. but its not executing as per requirement i.e. in simulation it only executes correctly for first i/p data and when i give next databyte it turns the o/p to be XX
why this is happening, can somebody help me?

 

[devas]

Hi,

Maybe you can post your code here. Without the code I have no idea what is happening with the for loop.

Devas

 

[melexia]

hi devas i have pasted the code below, this for loop is executing correctly for first time but when next pulse of gray_rst_i comes it shows XXXX , i have tried it doing without clk event also but result is same. plz check it and reply


-- binary(24) <= gray(24);

-- process(gray,binary,gray_rst_i,bi_rst,clk,rst)
-- variable i : integer;
-- begin
---- if rst = '1' or bi_rst = '1' then
---- binary(23 downto 0) <= "000000000000000000000000";
---- data_out <= "0000000000000000000000000";

---- elsif rising_edge(clk) then

-- if gray_rst_i = '1' then

-- for i IN 23 downto 0 loop
-- binary(i) <= binary(i+1) xor gray(i);
-- end loop;

-- else
-- binary(23 downto 0) <= "000000000000000000000000";
---- data_out <= binary;
-- end if;

---- end if;

-- end process;

 

[devas]

Hi,

The issue is that binary(24) stays 'U' and this ripples through all binary bits in the for loop.

I am not such an VHDL expert that I am sure my explanation why binary(24) stays 'U' is correct, but I guess it is due that the other binary bits are updated in the process. Signals do not update immediately but get an event flag and at the end of a process they are updated. I guess there is only one event flag for a signal and not event flags for individual bits of the signal. As binary(24) event flag is set in another process as binary(23 downto 0) event flag, the event flag of binary(24) is overruled and not seen.

You can change your code in something like this:

--process(bi_rst,clk,rst)
-- variable i : integer;
--begin
-- if rst = '1' or bi_rst = '1' then
-- binary(24) <= gray(24);
-- binary(23 downto 0) <= "000000000000000000000000";
-- data_out <= "0000000000000000000000000";
--
-- elsif rising_edge(clk) then
-- binary(24) <= gray(24);
--
-- if gray_rst_i = '1' then
--
-- for i IN 23 downto 0 loop
-- binary(i) <= binary(i+1) xor gray(i);
-- end loop;
--
-- else
-- binary(23 downto 0) <= "000000000000000000000000";
-- data_out <= binary;
-- end if;
--
-- end if;
--
--end process;

When you use a clocked process it is only necessary to have the clock and reset signals on the sensitivity list.

Devas

 

[dmk]

I see a few mistakes in your code.

1. The code-converter is a combinational circuit, so it doesn't need of a clock signal.
2. For ... Loop must start from lower-limit to upper-limit.
3. You must use variables for intermediate calculations.

So, your code sould be something like this:

process (bin_rst, gray_rst, gray)
variable b_tmp: std_logic_vector(WIDTH-1 downto 0);
begin
--if bin_rst='1' then
----bin_out <= (others=>'0');
--elsif gray_rst='1' then
----b_tmp(WIDTH-1):=gray(WIDTH-1);
----for tmp in 0 to WIDTH-2 loop
------b_tmp(WIDTH-2-tmp):=b_tmp(WIDTH-1-tmp) xor gray(WIDTH-2-tmp);
----end loop;
--else
----b_tmp := (others=>'0');
--end if;
--bin_out<=b_tmp;
end process;

Added after 1 minutes:

Forget to say - the WIDTH must be generic:
generic (WIDTH: natural := 3);

Added after 52 seconds:

or (in your case): generic (WIDTH: natural := 24);

 

[melexia]

hey devas,
as you said its true that whole signal updates on a event and not its bits separately. So I assigned binary(24) inside for loop itself and its working, thank you.

Added after 3 minutes:

hi dmk,
the mistakes you pointed out are ok for clk signal and variables but for loop is not bounded to be used with lower to higher range, it can be used with higher to lower also. and as devas said i made chnges and its working perfecltly.

Added after 2 minutes:

hey devas,
as you said its true that whole signal updates on a event and not its bits separately. So I assigned binary(24) inside for loop itself and its working, thank you.
one more thing that sensitivity list indicates that the process is dependant on these signals so whatever signals you will be using as a control to your process you have to add those in your sensitivity list or else it will just show a warning and not error.
Added after 3 minutes:

hi dmk,
the mistakes you pointed out are ok for clk signal and variables but for loop is not bounded to be used with lower to higher range, it can be used with higher to lower also. and as devas said i made chnges and its working perfecltly.

 

[dmk]

Yes, melexia, you are right for-loop, it's my mistake.

 

[Cutey]

for loop is strongley recommended specially when you want to implement the program try it with (if statement)