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For (i=8; i>=0; i = i - 1) from verilog to VHDL

Thread starter karper1986
Start date May 25, 2009

Status: Not open for further replies.

May 25, 2009

#1

K

karper1986

Member level 2

For from verilog to VHDL

Hi! I have a simple question -- how i can express these --> for (i=8; i>=0; i = i - 1) from verilog into VHDL? Thanks.

May 27, 2009

#2

S

shanmugaveld

Advanced Member level 4

For from verilog to VHDL

Usually we will use (VHDL)
for i in 0 to 8 loop
Am not tried the below logic

for i in 8 downto 0 loop

Status: Not open for further replies.

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