karper1986
Member level 2
For from verilog to VHDL
Hi! I have a simple question -- how i can express these --> for (i=8; i>=0; i = i - 1) from verilog into VHDL? Thanks.
Hi! I have a simple question -- how i can express these --> for (i=8; i>=0; i = i - 1) from verilog into VHDL? Thanks.