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Footprints, vias, and very thin substrates.. what's good?

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Full Member level 5
Nov 28, 2009
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Going into new ground for me, I seek hints on how to handle what looks like difficult choices when it comes to using circuit board substrates and surface mount packages at 10Ghz, without going into alumina hybrids and flip-chips. The device I have in mind is NE3511S02, but the same considerations apply to almost any microwave transistor.

The vendor information footprint used for s-parameter measurements is on 0.254mm (10mil) glass-PTFE Rogers 5880, about the thinnest available. It is soft stuff, hard to plate without sodium etch, has 50-Ohm lines 0.74mm wide.

There is a via directly under the package source connections, which is a no-no for reflow solderpaste soldering.

NE3511S03-footprint.jpeg NE3511S02-package.jpeg

The first thing I did was EM simulate the half-footprint attached to a source to discover the inductance of the set of vias, which includes one huge hole, leading to the question.. do single larger diameter vias lower the inductance faster than lots of tiny vias in parallel?

GIven there are 2 source tabs connected together, might there be a reason for having the underside clear, instead of placing a track right through between source pads, possibly helped by a via or two?

For design stability, we need a special amount of inductance in the source connection.

More - I want to make the substrate thicker - say 0.762mm (30 mil), in Er=3.5, where the 50 Ohm strips are 1.68mm wide, using a substrate (Taconic) where the strip loss is kept low from good underside surface finish.

Right now, it is making new via layouts that give that extra 100pH over the approx 30pH the vendor reference has, making new footprints that fit the strip widths for thicker board, and wondering how far I can mess with it before invalidate the s-parameter set.

I feel I may be knocking myself out doing stuff the hard way, but I can see no other good way. Advice from any who have been here before would be appreciated.

Man, there are substrates a lot thinner than 10 mils! Look at Megtron 6 material, for instance. I have used 2.3 mil thick layers for fine pitched leadless chip carriers. You need the thin substrate to be able to plate the small diameter laser drilled via holes in the solder pads.
Thanks for the reply.

I knew thinner substrates were available, but I was trying to contrive deliberate source inductance by using the thickness of the board to give some via length. The amount is small, but vital to stability. Too much is also no good. For me, the thicker, the stiffer, it is, then tolerances are not so critical, and it gets easier to manage.

For example, a 150 deg. radial stub on each source connection, peppered with 12 vias 0.4mm (about 16mil) outer diameter on 30mil substrate with 1oz. copper is still too much inductance. That is when I considered 20mil thick.

One end of the substrate gets involved with a waveguide transition, which is another factor driving the wish for wider trace.

The other end makes it to a coaxial connection, throwing away about 0.3 to 0.5dB, but that's OK because the gain is then available, but it gets more awkward mechanically as the substrate gets thinner.

I am thinking that if it has to be as thin as 2.3mils, then it had better come laminated to a piece of metal, or regular PCB.
Board makers I asked (UK) were OK to make holes to 0.3mm (about 12mil), or at a pinch 0.25mm (10mil), in 20mil thick Rogers or Taconic. These would be huge on a 2.3mil substrate.

The device packages are quite large, compared to what you deal with.

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