davyzhu
Advanced Member level 1
Hi all,
I want to folding Verilog code in GVIM.
The Verilog code clause is "begin"-"end" pair. Is there any tutorial talk about how to use the folding in GVIM? And does GVIM support "begin"-"end" pair folding? Thanks!
BTW, my GVIM version is 6.2.
Best regards,
Davy
I want to folding Verilog code in GVIM.
The Verilog code clause is "begin"-"end" pair. Is there any tutorial talk about how to use the folding in GVIM? And does GVIM support "begin"-"end" pair folding? Thanks!
BTW, my GVIM version is 6.2.
Best regards,
Davy