flop in verilog by non-blocking assignment

[ASIC_intl]

Hi

Suppose I am writing the RTL for a D-FLIP FLOP in Verilog. Generally inside the always block we write blocking assignment statement for a RTL of D flipflop. What will occur if I change it to a non-blocking assignment statement? Will it still synthesize to a flop? If yes, please let me know the difference between the two.

Regards,
Biswanath

 

[research_vlsi]

hi in ur case,if u use both blocking or non blocking in RTL, the synthesis tool will produce a D flip flop, thats sure.
But it is recommended to use Non Blocking for Sequential Design. And Blocking for combinational.
Since Flip flop is sequential use non blocking.

 

[FvM]

Usage of blocking statements may have either no effect at all or completely change the behaviour, depending on their order. The question can't be answered generally without considering your intended code.

As research_vlsi said, there is no sense in using blocking statements for a d-flip-flop. It has a purpose for particular design constructs only.

See for a detailed discussion.

 

[ASIC_intl]

Hi

But in usual text books when they write the code of a D-flop they use blocking assignments. I have never seen non-blocking assignment as you suggested.

Can u explain?

Added after 4 minutes:

Hi

The intended code here is the code of a D-flip flop only. The code contains an assignment statement which is blocking assignment after the always block as usual.

 

[tkkg3000]

Hi

In my opinion,we should use non-blocking for FF,and blocking for combinational logic.
There are many coding styles, many ways to use non-blocking and blocking assignment.However,the above-mentioned is the best way.

This is code is just for demonstration,I am not sure it is legal or not:

always@(posedge clock or negedge reset)
if(reset) {
q1<=1'b0;
q2<=1'b0;
}
else{
q1<=d1;
q2<=d2;
}

The result after synthesizing is 2 separate FFs.
If we change from non-blocking to blocking assignment,does it generate 2 separate FFs?I think it is not.

 

[sree205]

I've to reiterate what FvM has just said in the post above. blocking statement can either have no effect or change the behaviour depending on the order.

For the code posted by tkkg3000, even changing it to blocking statement infers D-flops in xilinx ise. i believe its because there is no dependency between the q1 and q2.