GARNETWILSON
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i have to design an adder module in verilog; input values are 0.1519 and -1.02123
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i have to design an adder module in verilog; input values are 0.1519 and -1.02123
And why is the second module using floating point and not fixed point?The output of the 1st module should be converted to floating point and feed to the 2nd module...I don't know how...
Seriously, you can't type this URL "https://www.xilinx.com" into your web browser! 8-OGARNETWILSON said:can you send me a link to learn about Xilinx IP core generator?