Floating nodes at CMOS usually refer to a transistor's gate that sees high impedance .The transistor's gate is of capacitive nature ,thus any charges can get trapped at this node .This may cause a transistor to be on will the designer thought that the transistor is off because no voltage is applied to the gate .This ambiguity (not being certain where the transistor is operating) is unwanted so the gate usually not left floating but os connected to a well defined voltage.