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You can share oxide diffusion to make them more compact. Sometimes bending poly can also help but this not recommended due to process constraints.
on second thoughts, optimizing the flip flop area may not necessarily give you a smaller area, routing spacing/density will start to affect the place and route.
disclaimer: my company (MunEDA) works in this field.
steadymind's post referred to layout optimization; in this case, your MOS widhts are given and all you want to do is optimum place&route.
We do circuit optimization: changing the devices' widths. Make some MOS 5% wider, others 10% more narrow, ... in order to improve delays, setup&hold times, power consumption, area. There are strong trade-offs. Many test benches and measurements are involved (many process corners, input slopes, output loads, ...) and must be optimized simultaneously.
See for example:
P. Tavares: Automated Numerical Resizing of Standard Cells in WiCkeD, MUGM 2012.
F. Adduci: Sizing of standard cells in worst-case process conditions in 110nm BCD9s, MUGM 2012.
You can register to see MUGM presentations at **broken link removed**
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