Hi
thanks for the reply
in terms of circuit design of FF's can you give me some guide lines...
any method to follow to design a standard cell FF for area optimization???
Thanks
disclaimer: my company (MunEDA) works in this field.
steadymind's post referred to layout optimization; in this case, your MOS widhts are given and all you want to do is optimum place&route.
We do circuit optimization: changing the devices' widths. Make some MOS 5% wider, others 10% more narrow, ... in order to improve delays, setup&hold times, power consumption, area. There are strong trade-offs. Many test benches and measurements are involved (many process corners, input slopes, output loads, ...) and must be optimized simultaneously.
See for example:
P. Tavares: Automated Numerical Resizing of Standard Cells in WiCkeD, MUGM 2012.
F. Adduci: Sizing of standard cells in worst-case process conditions in 110nm BCD9s, MUGM 2012.
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