flexible wire name ussing 2d array method?

[hangchiu]

Verilog-flexible wire name ussing 2d array method?

hello everyone,

I want to write a flexible design , so I need to set my variable by parameter like

wire [31:0] v_sum [0:`Y_FRAME_WIDTH -1];

[[[[My question is can I see this v_sum[0] as a wire with 32-bits ans then connect it to a module port?? ]]]]]]

(I want to use this variable like

wire [31:0] v_sum0; --------> v_sum[0]
wire [31:0] v_sum1; --------> v_sum[1]
wire [31:0] v_sum2;
wire [31:0] v_sum3;
...
wire [31:0] v_sum499; <assume `YFRAME_WIDTH=500
)

module00 u0_instance(......, v_sum[0]);
module01 u1_instance(......, v_sum[1]);
module02 u2_instance(......, v_sum[2]);
module03 u3_instance(......, v_sum[3]);...etc

why I ask this question is when I code like that and use ModelSim to simulate,

somehow v_sum[0], v_sum[1] .... will turn into unknown .

can anyone give me some hints or direction ....Thank you sincerely...