flash ram interface test bench

[kranthi_vlsi]

The Flash address output shall be asserted to a valid i/p address for not less than 200 ms before the Flash write enable rising edge and 3 ns after Flash write enable rising edge.[both flash address and write enable are o/p to the flash interface]
how to write this test case in vhdl.

 

[TrickyDicky]

I usually find that interfacing my fingers with a keyboard using a good text editor does wonders.